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Midterm Exam Questions: EE105, Spring 2005, Exams of Microelectronic Circuits

Midterm exam questions for the ee105 course in spring 2005. The questions cover various topics including mosfet circuits, integrated charge-storage elements, and ic resistors. Students are required to find equations, numerical values, sketch graphs, and identify operating regions.

Typology: Exams

2012/2013

Uploaded on 03/22/2013

sajeev
sajeev 🇮🇳

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Download Midterm Exam Questions: EE105, Spring 2005 and more Exams Microelectronic Circuits in PDF only on Docsity! 1 EE105, Spring, 2005, Midterm 1, Howe 1. MOSFET circuit [17 points] (a) [3 pts.] Assuming that the transistor is operating in saturation, find an equation for the drain current iD in terms of the input voltage vIN, the output voltage vOUT, and the device parameters. It is not necessary to substitute numerical values. (b) [4 pts.] For vIN = 1.5 V, (i) find the numerical value of the output voltage in Volts and (ii) verify that the transistor is saturated for this case. 2 (c) [3 pts.] For vIN = 0.5 V, (i) find the numerical value of the output voltage in Volts and (ii) identify the transistor’s operating region. (d) [4 pts.] Sketch the output voltage vOUT as a function of the input voltage vIN over the range 0 V ≤ vIN ≤ 2.5 V on the graph below. Note: the current source IS only works for vOUT > 0 V and is a short-circuit for vOUT = 0V. (e) [3 pts.] For a DC input voltage VIN = 1.5 V, find the numerical value of the transconductance gm. If you couldn’t solve part (b), you can assume that VOUT = 0.25 V for this part (not the correct answer to (b), of course). 5 (d) [3 pts.] Sketch the capacitance of the 20 x 20 µm2 thin-oxide area as a function of the voltage VAB on the graph below. Given: due to oxide charges, the threshold voltage is VTn = 4 V, the minimum capacitance of the structure is one-half the maximum capacitance, and the thermal equilibrium capacitance is three-quarters of the maximum. (e) [3 pts.] Sketch the capacitance Cba as a function of the voltage VAB on the graph below. Ignore the contribution of the overlap of the metal onto the thick-oxide regions. Cthin oxide [fF] VBA [V] 6 3. IC resistors [16 points] Process Sequence: 1. Starting material: boron-doped silicon wafer with a concentration of 2 x 1017 cm-3 2. Deposit a 0.2 µm (=200 nm) thick SiO2 layer 3. Pattern the oxide using the Oxide Mask (dark field) by etching it down to the silicon. 4. Implant the phosphorus with dose Qd = 2 x 1012 cm-2 and anneal to form a 50 nm- thick phosphorus-doped regions where the silicon is exposed. 5. Spin on photoresist and pattern with the Implant Mask (clear field). 6. Implant phosphorus with dose Qd = 2 x 1012 cm-2 and then etch off the photoresist. 7. Anneal to activate the second implant; the phosphorus regions remain 50 nm thick. 8. Deposit a 200 nm-thick SiO2 layer and pattern using the Contact Mask (dark field). 9. Deposit 200 nm of aluminum and pattern using the Metal Mask (clear field). 7 Given: mobilities for this problem are µn = 800 cm2/(Vs) and µp = 200 cm2/(Vs). The saturation electric field for electrons is Esat = 1.25 x 104 V/cm and their saturation velocity is vsat = 107 cm/s. Count the “dogbone” contact areas as 0.65 square for both resistors. (a) [4 pts.] Sketch the cross section A-A’ on the graph below after step 9. Identify all layers clearly. (b) [4 pts.] What is the sheet resistance R□ of the 0.2 µm long, 0.1 µm wide resistor? (c) [4 pts.] What is the maximum current Imax in µA through the 0.4 µm long, 0.05 µm wide resistor? R□ = Imax = µA
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