Download Transistor - Microelectronic Devices and Circuits - Solved Exam and more Exams Microelectronic Circuits in PDF only on Docsity! University of California at Berkeley
College of Engineering
Dept. of Electrical Engineering and Computer Sciences
EE 105 Midterm |
Spring 2005 Prof. Roger T. Howe March 2, 2005
Your Name: SOLUTIONS
Student 1D Number:
Guidelines
Closed book and notes; one 8.5” x 11” page (both sides) of your own notes is allowed.
You may use a calculator.
Do not unstaple the exam.
Show all your work and reasoning on the exam in order to receive full or partial credit.
Time: 80 minutes = I hour, 20 minutes.
Score
Points
Problem | Possible | Score
1 17
2 17
3 16
Total 50
1. MOSFET circuit [17 points}
Given:
Voup =2.5V E=05 pm
ne W=5 um
|e HrCax = 100 pA/V?
Vrmn=0.5V
rp ip =0 V2
v=0
+
Js= 125 pA
be
(a) [3 pts.] Assuming that the transistor is operating in saturation, find an equation for the
drain current ip in terms of the input voltage viv, the output voltage vour, and the
device parameters. It is not necessary to substitute numerical values.
by = BE ptn Coe (ite) (Ugg — Vin)”
ly = tb pinton (Wh) (in - Voor Vin)”
(b) [4 pts.] For vw = 1.5 V, (i) find the numerical value of the output voltage in Volts and
(ii) verify that the transistor is saturated for this case.
ok sme IT =O wd Ly-=O.
SB pn Ce CN) (iy - Your Vo)? = Ty = 12504
E lroepapey( Sos) (iy — Voge — 2-8)” = (250%
a 125aA '
(%- Vay, — 0,5 )™ = Sqm ay = EV
Mur OSV = OEY
Uy, = Ui -1V > ror = 1SV-tV 2 OSV G)
Vest: -
est the = Vip ~ Your = 2SV-O0.5V =2Vv
Baye ths — View = Yad ~ Voor -Vya = SV -0.5V -0.8V 20,5V
Vis > Vary, “> alah M (ti) 2
(b) [3 pts.] Find the numerical value of the junction capacitance Cjunction(O) between the
20 x 20 um? n-type region and the underlying p layer in thermal equilibrium (vg4 = 0
V) in fF. Given: 1 fF = 107° F. Hint: the information given in part (a) should be
very useful.
Cnet fo) - 2A & 23 0107? F fog?) (4-00 xo Send)
@)= ra ?pe 26 uwhe
= /48£F [ +4enlal Fa andl, the. Cer
(c) [4 pts.] Plot the junction capacitance versus vg, on the graph below. If you couldn’t
solve part (b), you can assume that the thermal equilibrium capacitance is 1000 fF in
order to do this part.
Cpnction EF],
1500
1250
1000
750
500
250}
144 baw
7 j_4 it 11 >
1 2 3 4 5 6 7 8 9 1
Vas, (V}
Creme (2 ty.
x: gor (*) Gis C0)
2 2
V /~ Vien y+ Vee
da = 4, ~Pe = 0.72
(d) [3 pts.] Sketch the capacitance of the 20 x 20 um? thin-oxide area as a function of the
voltage Vz on the graph below. Given: due to oxide charges, the threshold voltage is
Vp, = 4 V, the minimum n capacitance of the structure is s one-half the m Maximum
capacitance and ermaleq
maximum,
Veg ~~” I Gee [-262mv))= ©
Com et Coe = CAS 110 Tefon) 40000" $2)
ree, ~4
1500 70
“(380 fe
1250. |
1000 NY
750
500
250
rs rr rr
Vee EV]
(e) [3 pts.] Sketch the capacitance C;, as a function of the voltage Vg on the graph
below. Ignore the contribution of the overlap of the metal onto the thick-oxide
regions.
Cee (0) = Cpu (0) + Og. aye C0) = 149 + 1860
fe
Cra [HF] Cha) x Cofe + 690 fe = 1592 Pr
= FS fF See
3000 chnatel
Awe Ben
1500
> [oO
1 :
1
Ba
3. IC resistors [16 points}
Qg
O 0.140.263 0.4 65 66 0.702809 1.01112
x, [Km]
a Oxide Mask nl Contact Mask
(dark field) (dark field)
Implant Mask [7A Metal Mask
(clear field) VA (clear field)
ie 0.1 pm
Process Sequence:
Starting material. boron-doped silicon wafer with a concentration of 2 x 10"? cm®
Deposit a 0.2 um (= 200 nm) thick SiO, layer
Pattern the oxide using the Oxide Mask (dark field} by etching it down to the silicon.
Implant phosphorus with dose Qz= 2 x 10"? cm? and anneal to form a 50 nm-thick
phosphorus-doped regions where the silicon is exposed.
Spin on photoresist and pattern with the Implant Mask (clear field).
Implant phosphorus with dose Qa = 2 x 10”? cm? and then etch off the photoresist.
Anneal to activate the second implant; the phosphorus regions remain 50 nm thick.
Deposit a 200 nm-thick SiO. layer and pattern using the Contact Mask (dark field).
Deposit 200 nm of aluminum and pattern using the Metal Mask (clear field).
awh
OPN AM