Two Level - Microelectronic Devices and Circuits - Exam, Exams of Microelectronic Circuits

Download Two Level - Microelectronic Devices and Circuits - Exam and more Exams Microelectronic Circuits in PDF only on Docsity! EECS 105 Midterm #1: Spring 1997 Professor R.T. Howe (Total: 50 points) Question #1 Multi-layer Resistor Layout [18 points] The CAD layout for a two-level resistor is shown above; the patterns are shown separately below. Process Flow 0. Starting material: lightly doped n-type silicon wafer. EECS 105, Midterm #1, Spring 1997 EECS 105 1 1. Deposit .5 um of SiO2 and pattern using Mask 1. 2. Implant boron (dose Qa = 1014cm-2) and anneal to obtain a junction depth xj = 1 um. 3. Deposit .5 um of SiO2. 4. Deposit .5 um of polysilicon (sheet resistance 200 Ohms per square) and pattern using Mask 2. 5. Pattern .5 um oxide layer using Mask 3. 6. Deposit .5 um of SiO2 and pattern using Mask 4. 7. Deposit 1 um of aluminum and pattern using Mask 5. (a) [4 pts.] Find the numerical value of the sheet resistance of the implanted layer formed in step 2, given that the hole mobility in this layer is up = 150 cm2/(Vs) (b) [5 pts.] Accurately sketch the fabricated structure along the cross section A - A' for this CAD layout and process flow. Use the horizontal line below as the silicon surface. The vertical scale should be followed in sketching the deposited layers. Use the "dot" fill pattern from Mask 2 for polysilicon layer and the "slash' fill pattern from Mask 5 for metal layers. EECS 105, Midterm #1, Spring 1997 Question #1 Multi-layer Resistor Layout [18 points] 2 (c) [4 pts.] For VD = -12 V, the edge of the depletion region on the n-side of the junction is located at xn = 1.5 um. Plot the charge density p(x) for this reverse bias on the graph below. (d) [4 pts.] Plot the electric field E(x) that corresponds to the charge density in part (c) on the graph below. Your plot should have the numerical values for the field at x = 0 and the locations of the edges of the depletion region. EECS 105, Midterm #1, Spring 1997 Question #2 pn Junction Electrostatics [17 points] 5 (e) [3 pts.] Sketch the depletion capacitance Cj(VD) on the graph below. Given: for VD = -4V, the depletion region edge on the n-side of the junction is xn = 1 um. Clearly indicate any breakpoints where the capacitance function changes. Question #3 MOS Electrostatics [15 points] EECS 105, Midterm #1, Spring 1997 Question #3 MOS Electrostatics [15 points] 6 The electric field E0(x) in thermal equilibrium for an MOS capacitor is plotted above. The gate is made of an unknown metal and the substrate is uniformly doped silicon. (a) [4 pts.] What type (n or p) is the substrate? Justify your answer. (b) [4 pts.] What is the doping concentration in the substrate? (c) [4 pts.] What is the numerical value of the voltage drop Vox,o in thermal equilibrium? Hint: the electric field plot is all that you need! EECS 105, Midterm #1, Spring 1997 Question #3 MOS Electrostatics [15 points] 7