Download Computer Systems Architecture: Lecture 16 - Virtual Memory - Prof. Alan L. Sussman and more Assignments Computer Science in PDF only on Docsity! CMSC 411 Computer Systems Architecture Lecture 16 Virtual Memory Alan Sussman l @ d da s cs.um .e u Administrivia • Homework #4 due in 1 week, April 14 • Exam #2 pushed back to April 21 • Cache simulator project posted, due May 1 – CSIC Linuxlab account info handed out today • Start reading Ch. 6 (not 6.5) • 400 level lecture series today and tomorrow, CSIC 2117 at 5PM, sponsored by AWC CMSC 411 - 16 (some from Patterson, Sussman, others) 2 Two-Level Page Tables Each process needs its own address space! Two-level Page Tables 31 12 11 02122 32 bit virtual address P1 index P2 index Page Offset Top-level table wired in main memory Subset of 1024 second-level tables in main memory; rest are on disk or ll t d CMSC 411 - 16 (some from Patterson, Sussman, others) 3 una oca e Choosing page size • A large page size – keeps page table small. – reduces cache miss times, if accesses have locality – reduces start-up overhead in moving data from disk to memory f TLB i– means ewer m sses • but also – wastes memory (internal fragmentation) – increases the time to start up a program CMSC 411 - 16 (some from Patterson, Sussman, others) 4 VM and Disk: Page replacement policy Page Table ...1 0 useddirty 1 0 Dirty bit: page written. U d bit t t 0 1 1 1 0 0 Set of all pages se : se o 1 on any reference in Memory Tail pointer: Clear the used bit in the page table Head pointer Place pages on free Freelist list if used bit is still clear. Schedule pages with dirty bit set to Hardware Architect’s CMSC 411 - 16 (some from Patterson, Sussman, others) 5 be written to disk. Free Pagesrole: support setting dirty and used bits MIPS Address Translation: How does it work? “Physical Addresses” A0-A31 A0-A31Virtual Physical “Virtual Addresses” CPU Memory D0-D31 D0-D31 Translation Look-Aside Buffer Data (TLB) Translation Look Aside Buffer (TLB) - A small fully-associative cache of mappings from virtual to physical addresses TLB also contains protection bits for virtual address Fast common case Virt al address is in TLB CMSC 411 - 16 (some from Patterson, Sussman, others) 6 : u , process has permission to read/write it. The TLB caches page table entries Physical and virtual pages must be the same size! virtual address ff Physical frame address Page Table 2 page o 0 1 V=0 pages either reside on disk or have not yet been ll t d TLB 3 physical address page off CMSC 411 - 16 (some from Patterson, Sussman, others) 7 a oca e . OS handles V=0 “Page fault” 2 frame page 2 50 MIPS handles TLB misses in software (random replacement). Other machines use hardware. Common Organization CPU TLB L1 Cache Even a cache hit requires TLB translation first!Write Buffer L2 Cache Memory bus CMSC 411 - 16 (some from Patterson, Sussman, others) 8
