Download Verification of Pipelined Processors using SAT-based Bounded Model Checking and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! Verification of Pipelined Processors using SAT-based Bounded Model Checking Achutam Murarka Perm # 8730319 University of California, Santa Barbara Pipelined Processors...
¢ Modern Processors are all
pipelined...why?
Non- pipelined Processor
+1
Each instruction executes in one cycle!
slow ._.. SIOW ........... slow ......
Pipelines mean Problems • As the number of stages in the pipeline increase the overall complexity of the system increase. • Branch predictors need to be designed and speculative executions need to take place. • This speculative data cannot be committed to memory unless till very late in the pipeline. • Data Dependency: So more temporary memory registers are needed. Called Architectural registers and Physical registers. • Various Hazards like Data, Control and Structural Hazards now need to be taken care off. • Net Result: Verification of the processor becomes even more challenging…!!!!!!!!! • To add to that the ever decreasing Time-to-Market. The solution…SAT-based BMC • Given a propositional formula ø, the Boolean satisfiability problem posed on ø is to determine whether there exists a variable assignment, if it exists, is called a Satisfiability Assignment for ø and ø is said to be satisfiable. • Most Modern SAT solvers are based on DPLL Algorithm. (Davis-Putnam- Logemann-Loveland) DPLL Algorithm
sat-solve()
if preprocess() = CONFLICT then
return UNSAT:
while TRUE do
if not decide-next-branch() then
return SAT:
while deduce() = CONFLICT do
blevel = analyze-confiict():
if blevel = 0 then
return UNSAT:
backtrack (blevel):
done:
done:
Test Program Generation
Methodology
Processor Architecture
(Specification)
Fault
Model
Processor Properties
Model P
I l
/ “Decompose f “Decompose >,
\\Gfnecessary) / \ Gfaecessary) /
NN Negate 7
property, Decide
Me Vic
we
( SAT-ba sed)
\ BMC Pa
a
Test prograns
Functional Fault Model • The Pipelined Architecture is modeled as a graph G = (V, E) • V is the node. Units (Fetch, Decode, etc.) Storage (Register File, Memory, etc.) • E is the edge. Pipeline Edge (Solid Line) Data Transfer Edge (Dotted Line) Functional Fault Model
Cache
Graph Model of the MIPS processor
Design and Property
Decomposition
else PrimaryInputs = PrimaryInputs U inp,
endif
if TaskList is empty
TaskList = FutureList; FutureList = 6
endif
endwhile
test; = GenerateTest(PrimarylInputs).
TestPrograms = TestPrograms U testi
endfor
return TestPrograms
End
Property Generation • Every node fault is converted into a property F(Pi) where F is the temporal operator (eventually) and Pi is (activity of the ith module). • Negate it to represent it as G(~Pi). • F(Decode.stall) which means “Decode in stall” is converted into G(~Decode.stall) meaning “Decode never in stall”. Determination of the Bound • Maximum Bound is given by {FE -> DE -> IALU -> MEM -> Cache -> MM -> Cache -> MEM -> WB } • Bound for “FADD1 in operation execution” will be 3. (pipeline register between the pipeline stages) Results Comparison of Test Generation Techniques based on the Number of Interactions Future Work • The single most important achievement of SAT-based verification has been its emergence as an orthogonal technology to BDD-based model checking techniques. • Studies at Intel have shown that BMC has better capacity and productivity over UMC for real designs taken from the Intel series of processors. • The strength of SAT-based verification techniques lies primarily in Falsification. • BDD-based symbolic model checking continues to be the de-facto standard for verifying properties. • SAT-based applications cannot be applied to the problem of computing the sequential depth of a given system. (probably because of its inherent intractability of the problem) • For large sequential depths the method of unrolling the circuit into explicit time frames makes it unsolvable for large circuits with a high degree of sequential depth. • Therefore, further research needed to develop SAT-based model checking into a viable alternative to BDD-based symbolic model checking Thank You
