Verilog HDL Overview: Understanding the Differences between Verilog and VHDL, Slides of Verilog and VHDL

Download Verilog HDL Overview: Understanding the Differences between Verilog and VHDL and more Slides Verilog and VHDL in PDF only on Docsity! Verilog Overview An overview of the Verilog HDL. Docsity.com Lecture Overview • A perspective. • Some Verilog Basics • A couple of Verilog models Docsity.com The Verilog module • At the leaf of an architecture – module generic_unit (r,g0,g1,g2,g3,a,b); – output r; – input g0,g1,g2,g3,a,b; – assign r = (~a & ~b & g0) | (~a &b & g1) | – (a & ~b & g2) | (a & b & g3); – endmodule Docsity.com Its testbench • The Testbench to apply tests to the unit • Note the differences – No configuration – No declaration – Signals which retain a value are typed reg or wire – The #10 gives a 10ns delay – No signals in or out of this module like the VHDL testbench module vtb(); wire gout; reg a,b,g0,g1,g2,g3; generic_unit G1 (gout,g0,g1,g2,g3,a,b); initial begin #100 $finish; end initial begin #10 a=0; b=0; g0=1; g1=0; g2=0; g3=0; #10 a=0; b=0; g0=0; g1=0; g2=0; g3=0; #10 a=0; b=1; g0=0; g1=1; g2=0; g3=0; #10 a=0; b=1; g0=0; g1=0; g2=0; g3=0; #10 a=1; b=0; g0=0; g1=0; g2=1; g3=0; #10 a=1; b=0; g0=0; g1=0; g2=0; g3=0; #10 a=1; b=1; g0=0; g1=0; g2=0; g3=1; #10 a=1; b=1; g0=0; g1=0; g2=0; g3=0; end endmodule Docsity.com Another cut at the design – module generic_unit_m2(r,g0,g1,g2,g3,a,b); – output r; – input g0,g1,g2,g3,a,b; – wire t1 = ~a & ~b & g0; – wire t2 = ~a &b & g1; – wire t3 = a & ~b & g2; – wire t4 = a & b & g3; – assign r = t1 | t2 | t3 | t4; – endmodule Docsity.com And a structural slice • Can hierarchically model just like VHDL – module slice (r,cout,a,b,pctl,kctl,rctl,cin); – output r, cout; – input a,b,cin; – input [3: 0] pctl,kctl,rctl; – wire pint,kint; – generic_unit punit (pint,pctl[0],pctl[1],pctl[2], – pctl[3],a,b); – generic_unit kunit (kint,kctl[0],kctl[1],kctl[2], – kctl[3],a,b); – carry cunit (cout,pint,kint,cin); – generic_unit runit (r,rctl[0],rctl[1],rctl[2], – rctl[3],pint,cin); – endmodule Docsity.com Hierarchy • This slice could then be instantiated into the next higher level – the 8-bit architecture • Verilog does not have a generate statement – would have to wire it up explicitly • Levels of hierarchy are not limited Docsity.com Behavioral modeling and the always block • The alu behavioral model could also be done in Verilog – module alu_beh (a,b,cin,alu_op,r); – input [7:0] a,b; – input cin; – input alu_op; – output r; – // now start the modeling Docsity.com The always block • The always block executes whenever one of the signals in the list has a transition according to the way it is written • Could also write it with ANDs such that all the signals used must have a transition Docsity.com The register set • VHDL Model for a refresher • The Entity • LIBRARY IEEE; • USE IEEE.STD_LOGIC_1164.ALL; • ENTITY registers is • PORT ( ABUS,BBUS : INOUT std_logic_vector; • Aload,Bload : IN std_logic; • Adrive,Bdrive : IN std_logic; • AregNo,BregNo : IN integer); • END registers; Docsity.com The architecture • ARCHITECTURE behavioral OF registers IS • BEGIN • regs : PROCESS (Aload,Bload,Adrive,Bdrive) • TYPE reg_set_type is array (0 to 15) of std_logic_vector (ABUS'RANGE); • VARIABLE reg_set : reg_set_type; • CONSTANT HighImp : std_logic_vector (15 downto 0) := "ZZZZZZZZZZZZZZZZ"; • BEGIN • IF (Aload'EVENT and Aload = '1') -- Latch A bus into register • THEN reg_set(AregNo) := ABUS; • END IF; • IF (Bload'EVENT and Bload = '1') -- Latch B bus into register • THEN reg_set(BregNo) := BBUS; • END IF; • IF (Adrive'EVENT) • THEN • IF (Adrive = '0') -- Drive A register onto ABUS • THEN ABUS <= reg_set(AregNo); • ELSE ABUS <= HighImp; • END IF; • END IF; • IF (Bdrive'EVENT) • THEN • IF (Bdrive = '0') -- Drive B register onto BBUS • THEN BBUS <= reg_set(BregNo); • ELSE BBUS <= HighImp; • END IF; • END IF; • END PROCESS regs; Docsity.com Continued 2 – if (adrive = = 1) – case (aregno) – 4’b0000: abus = areg0; – … – endcase – // drive of b similar – endmodule Docsity.com Some general Verilog features • Propagation Delays – Single Delay: and #3 G1 (y,a,b,c); – Rise/Fall Delay and #(3,5) G2 (y,a,b) – Rise/Fall/Turnoff buff0 #(3,6.5) (y,x_in,en) – Rise/Fall/Turnoff with Min:typ:Max – buff1 #(3:4:5,4:5:6,7:8:9) (y,x_in,en); Docsity.com Verilog features • Built in value set for built in logic type – 0 1 x z – Organized as registers, nets (wires), and memories • Does have integer and real types • Does have procedures but few references to be found as to their use. They are declared in the module where used. Verilog does not have packages. • Several cites on web had similar figures to comparison figure given earlier Docsity.com