VHDL Basics: Understanding Entities, Architectures, and Terms, Slides of Computer Science

Download VHDL Basics: Understanding Entities, Architectures, and Terms and more Slides Computer Science in PDF only on Docsity! COE 405 VHDL Basics Docsity.com Outline • VHDL Terms • Design Entity • Design Architecture • VHDL model of full adder circuit – Behavioral model – Structural model • VHDL model of 1’s count circuit – Behavioral model – Structural model Docsity.com VHDL Terms … • Attribute: – Data attached to VHDL objects or predefined data about VHDL objects – Examples: • maximum operation temperature of a device • Current drive capability of a buffer • VHDL is NOT Case-Sensitive – Begin = begin = beGiN • Semicolon “ ; ” terminates declarations or statements. • After a double minus sign (--) the rest of the line is treated as a comment Docsity.com VHDL Models ... Docsity.com … VHDL Models PACKAGE DECLARATION PACKAGE BODY (often used functions, constants, components, …. ) ENTITY (interface description) ARCHITECTURE (functionality) CONFIGURATION (connection entity ↔ architecture) Docsity.com Entity Examples … • Entity FULLADDER is -- Interface description of FULLADDER port ( A, B, C: in bit; SUM, CARRY: out bit); end FULLADDER; FULL ADDER A B C SUM CARRY Docsity.com … Entity Examples • Entity Register is -- parameter: width of the register generic (width: integer); --input and output signals port ( CLK, Reset: in bit; D: in bit_vector(1 to width); Q: out bit_vector(1 to width)); end Register; D Q CLK Reset width width D Q Docsity.com … Design Entity Architectural Specs •Behavioral (Algorithmic , DataFlow) • Structural A B Z Name Basic Modeling Unit Interface Specs • Name • Ports (In, Out, InOut) • Attributes DESIGN ENTITY Docsity.com … Architecture Examples: Structural Description Entity HA is PORT (I1, I2 : in bit; S, C : out bit); end HA ; Architecture behavior of HA is begin S <= I1 xor I2; C <= I1 and I2; end behavior; Entity OR is PORT (I1, I2 : in bit; X : out bit); end OR ; Architecture behavior of OR is begin X <= I1 or I2; end behavior; Docsity.com One Entity Many Descriptions • A system (an entity) can be specified with different architectures Entity Architecture A Architecture B Architecture C Architecture D Docsity.com Example: Ones Count Circuit • Value of C1 C0 = No. of ones in the inputs A2, A1, and A0 – C1 is the Majority Function ( =1 iff two or more inputs =1) – C0 is a 3-Bit Odd-Parity Function (OPAR3)) – C1 = A1 A0 + A2 A0 + A2 A1 – C0 = A2 A1’ A0’ + A2’ A1 A0’ + A2’ A1’ A0 + A2 A1 A0 A0 A2 C0 A1 C1 Docsity.com Ones Count Circuit Architectural Body: Behavioral (Algorithmic) Architecture Algorithmic of ONES_CNT is begin Process(A) -- Sensitivity List Contains only Vector A Variable num: INTEGER range 0 to 3; begin num :=0; For i in 0 to 2 Loop IF A(i) = '1' then num := num+1; end if; end Loop; -- -- Transfer "num" Variable Value to a SIGNAL -- CASE num is WHEN 0 => C <= "00"; WHEN 1 => C <= "01"; WHEN 2 => C <= "10"; WHEN 3 => C <= "11"; end CASE; end process; end Algorithmic; Docsity.com Ones Count Circuit Architectural Body: Behavioral (Data Flow) • C1 = A1 A0 + A2 A0 + A2 A1 • C0 = A2 A1’ A0’ + A2’ A1 A0’ + A2’ A1’ A0 + A2 A1 A0 Architecture Dataflow of ONES_CNT is begin C(1) <=(A(1) and A(0)) or (A(2) and A(0)) or (A(2) and A(1)); C(0) <= (A(2) and not A(1) and not A(0)) or (not A(2) and A(1) and not A(0)) or (not A(2) and not A(1) and A(0)) or (A(2) and A(1) and A(0)); end Dataflow; Docsity.com Ones Count Circuit Architectural Body: Structural … • C1 = A1 A0 + A2 A0 + A2 A1 = MAJ3(A) • C0 = A2 A1’ A0’ + A2’ A1 A0’ + A2’ A1’ A0 + A2 A1 A0 = OPAR3(A) ONES_CNT C1 Majority Fun C0 Odd-Parity Fun AND2 NAND3 OR3 NAND4 Structural Design Hierarchy INV Docsity.com VHDL Structural Description of Majority Function SIGNAL A1, A2, A3: BIT; Declare Maj3 Local Signals begin -- Instantiate Gates g1: AND2 PORT MAP (X(0), X(1), A1); g2: AND2 PORT MAP (X(0), X(2), A2); g3: AND2 PORT MAP (X(1), X(2), A3); g4: OR3 PORT MAP (A1, A2, A3, Z); end Structural; Wiring of Maj3 Components Docsity.com VHDL Structural Description of Odd Parity Function … g3 g4 Z1 Z2 Z3 Z4 Z g1 g2 x(0) A0B x(1) A1B x(2) A2B X(2) A1B X(0) A1B g5 g6 g7 A0B A2B X(0) X(1) X(2) X(1) A2B A0B C0 Odd-Parity (OPAR3) g8 Architecture Structural of OPAR3 is Component INV PORT( I: in BIT; O: out BIT); end Component ; Component NAND3 PORT( I1, I2, I3: in BIT; O: out BIT); end Component ; Component NAND4 PORT( I1, I2, I3, I4: in BIT; O: out BIT); end Component ; Docsity.com VHDL Structural Description of Odd Parity Function SIGNAL A0B, A1B, A2B, Z1, Z2, Z3, Z4: BIT; begin g1: INV PORT MAP (X(0), A0B); g2: INV PORT MAP (X(1), A1B); g3: INV PORT MAP (X(2), A2B); g4: NAND3 PORT MAP (X(2), A1B, A0B, Z1); g5: NAND3 PORT MAP (X(0), A1B, A2B, Z2); g6: NAND3 PORT MAP (X(0), X(1), X(2), Z3); g7: NAND3 PORT MAP (X(1), A2B, A0B, Z4); g8: NAND4 PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural; Docsity.com