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Download vhdl cheat sheet vhdl cheat sheet vhdl cheat sheet and more Cheat Sheet Verilog and VHDL in PDF only on Docsity! VHDL Quick Reference Card 1. Introduction VHDL is a case insensitive and strongly typed language. Comments start with two adjacent hyphens (--) and end at end of line. 2. Compilation Units Library Usage Declarations -- ref. 11 Entity Declarations -- ref. 3 Architecture Declarations -- ref. 4 Package Declarations -- ref. 10 Configuration Declarations -- ref. 14 3. Entity Declaration entity n_input_nand is generic ( n : integer := 2); port ( data : in bit_vector( 1 to n ); result : out bit ); end n_input_nand -- port directions : in | out | inout | buffer | linkage 4. Architecture Declaration architecture behave of n_input_nand is -- declarations -- ref. 7 begin -- concurrent statements -- ref. 9 end behave 5. Operators logical operators : and, or, xor, nand, nor, xnor, not relational operators : =, /=, <, <=, >, >= shift left/right logical operators : sll, srl shift left/right arithmetic operators : sla, sra rotate lefet/right logical operators : rol, ror other operators : +, -, &, *, **, /, mod, abs, rem eg. & : concatenation, ‘1’ & “10” = “110” ** : exponentiation, 2 ** 3 = 8 rem : remainder, 7 rem 2 = 1 mod : division modulo, 5 mod 3 = 2 6. Data Types 6.1 Predefined Data Types bit ‘0’ and ‘1’ bit_vector Array of “bit” boolean true and false character 7-bit ASCII integer signed 32 bit at least natural integer >= 0 positive integer > 0 real Floating point, min : +1e38 to -1e38 string Array of characters time hr, min, sec, ms, us, ns, ps, fs 6.2 User Defined Data Types type range is range 0 to 100000 units meter; -- base unit kilometer = 1000 meter; end units distance; type number is integer; type voltage is range 0 to 5; type current is range 1000 downto 0; type d_bus is array ( range <> ) of bit; type instruction is record opcode : bit; operand : bit; end record; type int_file is file of integer; type pointer_to_integer is access integer; subtype positive_number is integer range 0 to 100000 type fourval is ( X, L, H, Z ); subtype resolve_n is resolve twoval; 7. Declarations constant bus_width : integer := 32 variable read_flag : bit := 0; -- only in processes -- and subprograms signal clock “ bit; file f3 : int_file open write_mode is “test.out”; alias enable : bit is addr(31); attribute delay : time; component n_input_nand generic ( n : integer := 2 ); port ( data : in bit_vector ( 1 to n ); result : out bit ); end component n_input_nand; function square ( i : integer ) return integer; for store : use configuration latch; 8. Attributes -- type my_array is array ( 9 downto 0 ) of any_type; -- variable an_array : my_array; -- type fourval is ( ‘0’, ‘1’, ‘Z’, ‘X’ ); -- signal sig : sigtype; -- constant T : time := 10 ns; Attribute Result type Result my_array’high any_type 9 my_array‘left any_type 9 my_array‘low any_type 0 my_array‘right any_type 0 my_array‘ascending boolean false my_array‘length integer 10 my_array‘range integer 9 downto 0 my_array‘reverse_range integer 0 to 9 fourval‘leftof(‘0’) fourval error fourval‘leftof(‘1’) fourval ‘0’ fourval‘pos(‘Z’) integer 2 fourval‘pred(‘1’) fourval ‘0’ fourval‘rightof(‘1’) fourval ‘Z’ fourval‘succ(‘Z’) fourval ‘X’ fourval‘val(3) fourval ‘X’ sig‘active boolean True if activity on sig sig‘delayed(T) sigtype Copy of sig delayed by T sig‘driving_value sigtype Value of driver on sig sig‘event boolean True if event on sig sig‘last_active time Time since last activity sig‘last_event time Time since last event sig‘last_value sigtype Value before last event sig‘quiet(T) boolean Activity ( now – T ) to now sig‘stable(T) boolean Event ( now – T ) to now sig‘transactio bit Toggles on activity on sig 9. Statements 9.1 Concurrent Statements state_mach : process ( state ) -- label is optional -- variable declarations -- ref. 7 begin -- sequential statements -- ref. 9 end process; U1_n_input_nand : n_input_nand generic map ( n => 2 ) port map ( data => my_data; result => my_res ); top_block : block -- declaration -- ref. 7 begin -- concurrent statements -- ref. 9 end block; label1 : for i in 1 to 3 generate label2 : nand2( a(i), b(i), c(i) ); end generate label3 : if ( i < 4 ) generate label4 : nor2( a(i), b(i), c(i) );