VHDL Language Elements - Intro to Advanced Digital Design - Lecture Slides, Slides of Digital Systems Design

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L13 – VHDL Language Elements Docsity.com VHDL Language Elements • Elements needed for FPGA design – Types • Basic Types • Resolved Types – special attributes of resolved types – Concurrent Statements – Sequential Statements – Design Units – Packages • Ref: text Unit 10, 17, 20 Docsity.com Enumeration Types • Predefined – TYPEs BIT and BOOLEAN • Enumeration types initialize to the leftmost element of the set for signals and variables declared to be of the type. • Other Examples – User defined – TYPE opcode IS (op0,op1,opOR,opAND, opNOT, opXOR,opXNOR,opADD,opSUB, opINC,opDEC); • Usage – SIGNAL instr : opcode; – VARIABLE mybit : BIT; Docsity.com Other types • Integer – TYPE INTEGER – range is at least 32 bit 2’s complement • Character – TYPE CHARACTER – single ASCII characters • Real numbers – TYPE REAL – floating point type – IEEE standard Docsity.com Physical Types • Predefined – TYPE time IS RANGE 0 to 1E18 • UNITS – FS; -- femtosecond – PS = 1000 FS; -- picosecond – NS = 1000 PS; -- nanosecond – US = 1000 NS; -- microsecond – MS = 1000 US; --millisecond – SEC = 1000 MS; -- second – MIN = 60 SEC; -- minute • END UNITS; Docsity.com Composite types • ARRAYS – TYPE my_word IS ARRAY (0 to 31) of BIT; – TYPE regs IS ARRAY (7 downto 0) of my_word; • Unconstrained ARRAYS – TYPE memory IS ARRAY (INTEGER range <>) of my- word; – USE: • VARIABLE my_mem : MEMORY (0 to 65536); Docsity.com Predefined Arrays • SUBTYPE positive IS INTEGER range 1 to ITEGER’HIGH; – INTEGER’HIGH is the largest integer for this installation • TYPE string IS ARRAY (POSITIVE RANGE <>) of CHARACTER; • SUBTYPE natural IS INTEGER range 0 to ITEGER’HIGH; • TYPE bit_vector IS ARRAY (NATURAL range <>) of BIT; Docsity.com Some examples • EXAMPLES of use – VARIABLE message : STRING(1 to 17) := “THIS is a message”; – Text inside a string is case sensitive – message (1 to 16) := “Modified Message”; • WHAT WOULD BE CONTAINED IN THE VARIABLE MESSAGE???? – SIGNAL low_byte : BIT_VECTOR (0 to 7); – SIGNAL fword : BIT_VECTOR (15 downto 0); Docsity.com Declarations • VARIABLES – For use in processes, procedures and functions – Scope limited to the process, procedure, or function in which declared. – Cannot be declared in the declarative region of architectures!!!! – Have no time component – Any assignment takes place immediately upon assignment. • VARIABLE my_var : BIT; – Sometimes used in synthesis Docsity.com Declarations • ALIASES – SIGNAL real_num : BIT_VECTOR (0 TO 31); – ALIAS sign : BIT is real_num(0); – ALIAS exp : BIT_VECTOR(0 TO 7) is real_num (1 TO 8); – ALIAS fract : BIT_VECTOR (0 to 23) is real_num (9 TO 31); • Then in the design you can assign or use any of the names real_num, sign, exp, fract. Docsity.com Declarations • CONSTANTS – CONSTANT pi : REAL := 3.141592; – CONSTANT cycle_time : TIME := 75 ns; – Can be declared and used but cannot be assigned to • COMPONENT – Declaration needed for hierarchical models – COMPONENT local_component_name • PORT(port declarations from component’s entity) – END COMPONENT; – The easy way to do a component declaration is to copy the ENTITY Declaration, change ENTITY TO COMPONENT, delete the IS and change END xxx to END COMPONENT – Once declared, the COMPONENT must be configured Docsity.com Size of Q76? • The size of the concatenated vector MUST match the size of the target. • Q76 – Could be 0 to 33 – OR 33 downto 0; Docsity.com More operators • SIGN:: + | - • MULTIPLYING:: * | / | MOD | REM – * and / can be used for integer and real – MOD and REM are valid only for type integer • MISCELANOUS:: ** | ABS | NOT Docsity.com Concurrent statements • Concurrent statements are those that can appear between the BEGIN and END of an architecture. • With these statements you model the component or system to be modeled. • These statements have semantic meaning and execute independent of the order in which they appear in the model. • These statements – Boolean equations – synthesize well. Docsity.com Declaration of component • ARCHITECTURE use_it OF xyz IS – COMPONENT wigit • PORT(p1, p2 : IN BIT); – END COMPONENT: – -- and the configuration is – FOR C0 : wigit USE ENTITY work.wigit(y); – FOR OTHERS : wigit USE ENTITY work.wigit(Z); • Note that the component declaration is the same as the ENTITY declaration except that ENTITY becomes COMPONENT and it is END COMPONENT Docsity.com The instantiation – SIGNAL A,B,C,D : BIT; • BEGIN – CO : wigit PORT MAP (A, B); – C1 : wigit PORT MAP (p1 =>C, p2=>D); Docsity.com What about repetitive structures? • When you have repetitive structures to build up with instantiations • GENERATE STATEMENT – automates the instantiation of repetitive structures • • • Leftmost Unit Rightmost UnitInner Units Docsity.com Start of ARCHITECTURE • ARCHITECTURE iterative OF byte_comparator IS – --do component declaration and configuration – COMPONENT bit_comparator • PORT (a,b,gt,eq,lt:IN bit;a_gt_b, a_eq_b, a_lt_b:OUT bit); – END COMPONENT; – FOR ALL: bit_comparator USE ENTITY WORK.bit_comparator(bit_comp_arch); – --internal signal to connect bit positions – SIGNAL igt,ieq,ilt : bit_vector (0 to 6); Docsity.com 8 Component instantiations • BEGIN – C0 : bit_comparator PORT MAP (a(0),b(0),gt,eq,lt,igt(0),ieq(0),ilt(0)); – C1 : bit_comparator PORT MAP (a(1),b(1),igt(0),ieq(0),ilt(0),igt(1),ieq(1),ilt(1)); – C2 : bit_comparator PORT MAP (a(2),b(2),igt(1),ieq(1),ilt(1),igt(2),ieq(2),ilt(2)); – C3 : bit_comparator PORT MAP (a(3),b(3),igt(2),ieq(2),ilt(2),igt(3),ieq(3),ilt(3)); – C4 : bit_comparator PORT MAP (a(4),b(4),igt(3),ieq(3),ilt(3),igt(4),ieq(4),ilt(4)); – C5 : bit_comparator PORT MAP (a(5),b(5),igt(4),ieq(4),ilt(4),igt(5),ieq(5),ilt(5)); – C6 : bit_comparator PORT MAP (a(6),b(6),igt(5),ieq(5),ilt(5),igt(6),ieq(6),ilt(6)); – C7 : bit_comparator PORT MAP (a(7),b(7),igt(6),ieq(6),ilt(6),a_gt_b,a_eq_b, a_lt_b); • END; Docsity.com Generate version1 • Use component instantiations to handle boundries • BEGIN – --start with lsb where lsb is rightmost bit – C0: bit_comparator PORT MAP(a(0),b(0),gt,eq,lt,igt(0),ieq(0),ilt(0)); – C1to6: FOR i IN 1 to 6 GENERATE • C: bit_comparator PORT MAP (a(i),b(i),igt(i-1),ieq(i-1),ilt(i-1), igt(i),ieq(i),ilt(i)); – END GENERATE; – --end with msb where msb is leftmost bit – C7: bit_comparator PORT MAP – (a(7),b(7),igt(6),ieq(6),ilt(6),a_gt_b,a_eq_b,a_lt_b); • END iterative; Docsity.com