VHDL Tutorial: Understanding Behavioral and Structural VHDL with Examples, Study notes of Electrical and Electronics Engineering

Download VHDL Tutorial: Understanding Behavioral and Structural VHDL with Examples and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! VHDL Tutorial Behavioral VHDL 4 to 1 Mux library ieee; use ieee.std_logic_1164.all; entity MUX41 is port --define inputs and outputs ( S1 : inbit; -- input S1 S0 : inbit; D3 : in bit; D2 : in bit; D1 : in bit; D0 : in bit; Y : out bit -- output Y, note: NO ‘;’ used on the last line ); end MUX41; architecture logic of MUX41 is -- Note MUX41 is the same as entity name above begin Y <= (D0 and (not S1) and (not S0)) or (D1 and (not S1) and S0 ) or (D2 and S1 and (not S0)) or (D3 and S1 and S0 ) ; end logic; -- Note matching names ‘logic’ 4 to 1 Mux (S1 and S0 active low / Mixed Logic) library ieee; use ieee.std_logic_1164.all; entity MUX41 is port ( S1_L, S0_L, D3, D2, D1, D0 : in std_logic; --std_logic same as bit, multiple inputs of the same type can be defined on the same line separated by commas Y : out std_logic ); end MUX41; architecture logic of MUX41 is signal S1, S0 : std_logic; --define signals. Signals are like temp variables which are not defined in entity but are needed for the behaviour begin S1 <= not S1_L; --relating S1 to S1_L; S0 <= not S0_L; -- No _L in equation below since logic equation does not change Y <= (D0 and (not S1) and (not S0)) or (D1 and (not S1) and S0 ) or (D2 and S1 and (not S0)) or (D3 and S1 and S0 ) ; end logic; 2 to 1 Mux (using IF/ELSE) library ieee; use ieee.std_logic_1164.all; entity MUX2to1 is port( A, B: in std_logic_vector(7 downto 0); Sel: in std_logic; Y: out std_logic_vector(7 downto 0)); end MUX2to1; architecture behavior of MUX2to1 is begin process (Sel, A, B) -- rerun process if any changes, sensitivity list, all inputs begin if (Sel = '1') then Y <= B; else Y <= A; end if; -- note that *end if* is two words end process; end behavior; Note:  Std_logic_vector used to define a signal of more than 1 bit. In this case A, B and Y are all 8 bits and can be referred to as a vector or as individual components such as A(7), A(6),.. etc