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Virtual Memory and Memory Hierarchy, Study notes of Computer Architecture and Organization

Virtual memory and memory hierarchy. It explains the concept of indirection and how it is used in computer science. It also describes the memory hierarchy and caching, including registers, L1/L2 cache, main memory, virtual memory, and secondary storage. The document further explains magnetic disks and flash drives, their performance, and how they store bits. Finally, it discusses virtual address spaces and how they are broken into blocks called pages.

Typology: Study notes

2022/2023

Uploaded on 05/11/2023

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&�rgggkk+��,,,$��Q� �={�o��L��B��l�� ����wvvv���/777=z��/������7<uwvv=z�sr���,..�����L������H�zb��...�o<�ǡ�^����U��{��?��o�ե��N]&�J%q�.\���ˆo���L� 6���$�݃&�ҕ���3����t�PBHRΜ9��E���|&7�T��<�Riqq1��7���n���`g��9e����t��K��];.�p�6���bgg���ۋ���6~mm��ݻ]jUGtd���S�?�BESsܬ��%�7��]��8�wvv����"�IxbS� O)��Ԅt�����]h���[��i��6�SQH��"�K�?����������I�{ }&��� ���Kk�z��ѣG���'�&��S��;�W�LN?�{w����"JM�5�٭D$��W��Ϧ>T5;v�M;;;?��牸JbHK�����?e}�������K�#�N��m��إ��ͻw驪���P��x8 ��eB��D�!���.=2"��τ��222κ�����ܿ��;-r�3�f�N��ԦMi���P�"`yy��/,,ܾ};�����D_2,qd�+.���^[[ka��1/Y�Mz��z���z]�󬭭�ær���+:����@\�/�+=���L��"���7�###�����fh���_*�������j�YXX��,[.�N���{���Թ��U*�t������T*-..6��>199Y�����~�={V�c���$��h8g�h������n8V%K��V?P8u�Ra8@"�+��SSSቡ�ayy9q&��o�Ӫt�j����u���Ԁ��Wq�;�w�777 ��Rj�N�A^���T�������΃���ҽ�6��tJ�إ�����LM�� ���.��T�^\\�?\-$���QB�3�^W�<!ɭoRò�0�Ԯ�d;�5���2@_k8}@���j;�EtC���J�233S�۰tEmq��������ދ;| ������tN������ ғ��xVϤ��(>�o�'��NcґV�t�ix������r�f�wW�.��<����I�ejj��� ����������_w=��ahhhff��.������ӕP9�_ťR���É���_~)x�f-��A333�����T�Ն�C����� jyAM�#����P&����3g�ԟ*���t0�w��ԙ\kj��<�Y�ggg^�៘����1\��@t�/}��ie��xd����i@7LNN�����\�#��_��ⷫ�X��GңK�$��N&�/��S8���JE�Bdhh��ٳ {��ryvv6� �������D�/�nWBXN%����l�������Կ9��R�*N����N��T�����ٳg�g*��L�]�IWK�ì��$�ԡ��DPcat: /app/work/document/fa5183488b964802b2239c9224486966.txt.output_1.text: No such file or directory 9.2 Indirection • Indirection means using one entity to refer to another • Examples: – A variable name vs. it's physical memory address – Phone number vs. cell tower location/phone ID – Titles like "CEO" or "head coach" are virtual titles that can be applied to different people at different times • The benefits are we can change one without changing the other – We can change the underlying implementation without changing the higher level task. For example, a job description would read "The CEO shall perform this duty or that." and it need not be changed if the company replaces John Doe with Jane Doe. • "All problems in computer science can be solved by another level of indirection" – attributed to David Wheeler cat: /app/work/document/fa5183488b964802b2239c9224486966.txt.output_2.text: No such file or directory 9.5 Memory Hierarchy & Caching • Lower levels act as a cache for upper levels Disk / Secondary Storage ~1-10 ms Main Memory ~ 100 ns L2 Cache ~ 10ns L1 Cache ~ 1ns Registers L1/L2 is a “cache” for main memory Virtual memory provides each process its own address space in secondary storage and uses main memory as a cache This Photo by Unknown Author is licensed under CC BY-SA 9.6 Secondary Storage: Magnetic Disks • Magnetic hard drive consists of – Double sided surfaces/platters (with R/W head) – Each platter is divided into concentric tracks of small sectors that each store several thousand bits • Performance is slow primarily due to moving mechanical parts Surfaces Read/Write Head 0 Read/Write Head 7 Read/Write Head 1 … Track 0 Track 1 Sector 0 Sector 1 Sector 2 • Seek Time: Time needed to position the read-head above the proper track • Rotational delay: Time needed to bring the right sector under the read-head • Depends on rotation speed (e.g. 5400 RPM) • Transfer Time: • Disk Controller Overhead: 3-12 ms 5-6 ms 0.1 ms + 2.0 ms ~20 ms 9.7 Secondary Storage: Flash • Flash (solid-state) drives store bits using special transistors that retain their values even when power is turned off • Performance is higher than magnetic disks but still slower comparted to main memory – Better sequential read throughput • HD (Magnetic): 122-204 MB/s • SSD: 210-270 MB/s – MUCH better random read • Max latency for single read/write: 75us • When many requests present we can overlap and achieve latency of around 26us (1/38500) • Flash drives "wear-out" after some number of writes/erasures OS:PP 2nd Ed. Fig. 12.6 Intel 710 SSD specs. 9.10 Virtual Address Spaces (VAS) • Virtual address spaces (VASs) are broken into blocks called "pages" • Depending on the program, much of the virtual address space will be unused • Pages can be allocated "on demand" (i.e. when the stack grows, etc.) • All allocated pages can be stored in secondary storage (hard drive) 0 1 2 3 Unalloc 0 1 2 Unalloc Secondary Storage … Unalloc … 0 1 2 3 0 1 2 Used/Unused Blocks in Virtual Address Space Code 0x00000000 0xffff ffff Mapped I/O - Program/Process 1,2,3,… - Data - Heap - Stack - 0xc0000000 0x10000000 0 - Code 1 - Code 2 - Data 4 - Heap … 3 - Stack 0 - Code 1 - Code 2 - Data 4 - Heap 3 - Stack 9.11 0 1 2 3 Unalloc 0 1 2 Unalloc … Unalloc … 0 1 2 3 0 1 2 0 - Code 1 - Code 2 - Data 4 - Heap … 3 - Stack 0 - Code 1 - Code 2 - Data 4 - Heap 3 - Stack Physical Address Space (PAS) • Physical memory is broken into page-size blocks called "frames" • Multiple programs can be running and their pages can share the physical memory • Physical memory acts as a cache for pages with secondary storage acting as the backing store (next lower level in the hierarchy) • A page can be: – Unallocated (not needed yet…stack/heap) – Allocated and residing in secondary storage (Uncached) – Allocated and residing in main memory (Cached) 0x00000000 0x3fffffff 1GB Physical Memory and 32-bit Address Space 0xffffffff Secondary Storage Fictitious Virtual Address Spaces frame 0-Code Pg. 0 Pg. 2 2-Data Pg. 0 frame I/O and un- used area 9.12 Paging • Virtual address space is divided into equal size "pages" (often around 4KB) • Physical memory is broken into page frames (which can hold any page of virtual memory and then be swapped for another page) • Virtual address spaces can be contiguous while physical layout is not Physical Frame of memory can hold data from any virtual page. Since all pages are the same size any page can go in any frame (and be swapped at our desire). 0x00000000 0x3fffffff frame 0-Code Pg. 0 Pg. 2 2-Data Pg. 0 frame I/O and un- used area 0xffffffff Pg. 0 Pg. 1 Pg. 2 Pg. 3 unused … Pg. 0 Pg. 1 Pg. 2 unused unused … Phys. Addr. Space Proc. 1 VAS Proc. 2 VAS 9.15 VM Design Implications • SLOW secondary storage access on page faults (100us - 10ms) – Implies page size should be fairly large (i.e. once we’ve taken the time to find data on disk, make it worthwhile by accessing a reasonably large amount of data) – Implies the placement of pages in main memory should be fully associative to reduce conflicts and maximize page hit rates – Implies a "page fault" is going to take so much time to even access the data that we can handle them in software (via an exception) rather than using HW like typical cache misses – Implies we should use a write-back policy for pages (since write- through would be too expensive) 9.16 ADDRESS TRANSLATION Page Tables cat: /app/work/document/fa5183488b964802b2239c9224486966.txt.output_16.text: No such file or directory 9.17 Page Size and Address Translation • Since pages are usually retrieved from disk, we size them to be fairly large (several KB) to amortize the large access time • Virtual page number to physical page frame translation performed by HW unit = MMU (Mem. Management Unit) • Page table is an in-memory data structure that the HW MMU will use to look up translations from VPN to PPFN Offset within pageVirtual Address Virtual Page Number 31 12 11 0 Offset within pagePhysical Address Phys. Page Frame Number 31 30 12 11 0 00 Copied 12 Translation Process (MMU + Page Table) 29 20 18 0 0 0 0 2 0 0 0 0 0 2 1 b 0 0 0 Lookup VPN 0x00040 to it lives in PPFN: 0x0021b 9.17 Page Size and Address Translation • Since pages are usually retrieved from disk, we size them to be fairly large (several KB) to amortize the large access time • Virtual page number to physical page frame translation performed by HW unit = MMU (Mem. Management Unit) • Page table is an in-memory data structure that the HW MMU will use to look up translations from VPN to PPFN Offset within pageVirtual Address Virtual Page Number 31 12 11 0 Offset within pagePhysical Address Phys. Page Frame Number 31 30 12 11 0 00 Copied 12 Translation Process (MMU + Page Table) 29 20 18 0 0 0 0 2 0 0 0 0 0 2 1 b 0 0 0 Lookup VPN 0x00040 to it lives in PPFN: 0x0021b 9.20 Page Tables • VA is broken into: – VPN (upper bits) + Page offset: Based on page size (i.e. 0 to 4K-1 for 4KB page) • MMU uses VPN & PTBR to access the page table in memory and lookup physical frame (i.e. like an array access where VPN is the index: PTBR[VPN] ) – Each entry is referred to as a Page Table Entry (PTE) and holds the physical frame number & bookkeeping info • Physical frame is combined with offset to form physical address • For 20-bit VPN, how big is the page table? (See below) VAOffset w/in pageVirtual Page Number 31 12 11 0 Page Table Size = 220 entries * 18 bits = approx. 220*4bytes = 4MB PTBR = Page Table Base Reg. Offset w/in page PAPhys. Frame # 31 12 11 0 00 PTE Page Frame Number PTE … Other flags 20 Page Table in Main Memory 18 Processor 0xc0008000 0xc0008000 PTBR[2] PTBR[1] PTBR[0] … 0x0021b 0x0021b 0x00002 0x2d8 0x2d8 9.21 Page Table Example • Suppose a system with 8-bit VAs, 10-bit PAs, and 32-byte pages. VPN P1-VAS 0 1 2 3 4 5 6 7Page Table VA OffsetVPN 7 0 Offset PA PFN 4 0 4 9 Page Table 0x00 0x1F 0x20 0x3F 0x40 0x5F 0xE0 0xFF PFN Phys Mem 0 VP 3 1 2 VP 1 3 PT for P1 (OS Owns) 31 VP 5 0x000 0x01F 0x020 0x03F 0x040 0x05F 0x3E0 0x3FF V Entry 0 0 0x1a 1 1 0x02 2 1 0x18 3 1 0x00 4 0 0x10 5 1 0x1F 6 0 0x15 7 0 0x0A 9.22 Page Table Exercise • Suppose a system with 8-bit VAs, 10-bit PAs, and 32-byte pages. • Fill in the table below showing the corresponding physical or virtual address based on the other. If no translation can be made, indicate "INVALID" V Entry 0 0 0x0E 1 1 0x1E 2 1 0x16 3 1 0x06 4 0 0x0B 5 1 0x1F 6 0 0x15 7 0 0x0A Page Table VA PA 0x2D = 0010 1101 0x3CD 0x7A = 0111 1010 0x0DA 0xEF = 1110 1111 INVALID 0xA8 = 1010 1000 0x3E8 VAOffsetVPN 7 0 Offset PAPFN 4 0 4 9 Page Table 9.25 Multi-level Page Table Concept • Much of the VAS is often unused (gray areas in the image on the right) which implies many of the page table entries would be unused • Can we reduce the page table size and still do a lookup in constant time? – Do you have friends from every area code? – Likely contacts are clustered in only a few area codes. • Use a 2-level organization – 1st level LUT is indexed on area code and contains pointers to 2nd level tables – 2nd level LUT’s indexed on local phone numbers and contains contact ID entries • The first level is often called the page directory and while the 2nd level is the called page tables – PDE's (Page Directory Entries) contain pointers to 2nd level Page Tables LUT indexed w/ all possible phone #’s null … … 000 213 323 1st Level Index = Area Code (Page Directory) Area Code null000-000-0000 .. … null 000213-745-9823 999-999-9999 … 213 Table 2nd Level Index = Local Phone # 000-0000 999-9999 323 Table 000-0000 999-9999 If only 2 area codes used then only 1000 + 2(107) entries rather than 1010 entries 9.26 Analogy for Page Tables • Could extend to 3 levels if desired – 1st Level: Indices are area codes and values are pointers to 2nd level tables – 2nd Level: Indices are first 3-digits of local phone and values are pointers to 3rd level tables – 3rd Level: Indices are last 4-digits of local phone and values are contact ID’s (i.e. Translations) null … … 000 213 323 1st Level Index = Area Code Area Code … 2nd Level Index = Local Phone # 000 999 000 999 323 Table 213 Table null null 740 821 null null 3rd Level Index = Local Phone # 0000 9999 213-740 Table null 003 null 9823 0000 9999 323-821 Table null 248 null 7104 9.27 Multi-level Page Tables • Think of a multi-level page table as a tree – Internal nodes contain pointers to other page tables – Leaves hold actual translations 0x40 0x0400x35 Virtual Addr VPN offsetIdx1 Idx2 7 bits 7 bits 12 bits 0xd0000 PDBR/CR3 … … 0x3f 6 bits Idx3 [0x40] PT2[] = start addr PD start addr [0x3f] [0x35] PT3[] = start addr Level 1 Level 2 Level 3 Phys. Frame Addr Translations live in this level Processor • Unused entries in one level mean no table at the next (saving space) Page Directory 9.30 Page Faults Uncached Page Uncached Page Uncached Page Uncached Page Uncached Page Uncached Page 0 1 2 1023 0 1 2 1023 0 1 2 1023 0 1 2 1023 Offset w/in page Level Index 1 31 12 11 022 21 Level Index 2 1010 Pointer to start of 2nd Level Table PPFN’s frame I/O and un- used area frame 0x0 When HW encounters a PTE whose page is not in physical memory, it will generate a page fault exception and the OS will take over and retrieve the page before resuming the program. ee USC Viterbi C2 Multi-level Page Tables * Think of a multi-level page table as a tree — Internal nodes contain pointers to other page tables — Leaves hold actual translations me Unusedientrics injone level mean no table at VPN Processor the next (saving space) — 4——_ Idx1 Idx2_ Idx3_— offset 6bits 7bits 7bits 12 bits 0x3F | 0x40 | 0x35 /0x040] | oxdooo0 + I | | PDBR/CR3 PD start addr Page Directory PT2[] = start addr A) [0x40] Virtual Addr Level 1 pT3[}=startaddr Level 2 Level 3 Translations live in this level Phys. Frame Addr 9.31 Page Fault Steps • What happens when you reference a page that is not present? • HW will… – Record the offending address and generate a page fault exception • SW (the OS) will… – Pick an empty frame or select a page to evict – Writeback the evicted page if it has been modified • May block process while waiting and yield processor – Bring in the desired page and update the page table • May block process while waiting and yield processor – Restart the offending instruction • Key Idea: Handler can bring in the page or do anything appropriate to handle the page fault – Allocate a new page, zero it out, retrieve from secondary storage, etc. 9.30 Page Faults Uncached Page Uncached Page Uncached Page Uncached Page Uncached Page Uncached Page 0 1 2 1023 0 1 2 1023 0 1 2 1023 0 1 2 1023 Offset w/in page Level Index 1 31 12 11 022 21 Level Index 2 1010 Pointer to start of 2nd Level Table PPFN’s frame I/O and un- used area frame 0x0 When HW encounters a PTE whose page is not in physical memory, it will generate a page fault exception and the OS will take over and retrieve the page before resuming the program. 9.32 Page Replacement Policies • Possible algorithms: LRU, FIFO, Random • Since page misses are so costly (slow) we can afford to spend sometime keeping statistics to implement pseudo-LRU • HW will implement simple mechanism that allows SW to implement a pseudo-LRU algorithm – HW will set the “Referenced” bit when a page is used – At certain intervals, SW will use these reference bits to keep statistics on which pages have been used in that interval and then clear the reference bits – On replacement, these statistics can be used to find the pseudo-LRU page • Other simpler replacement algorithms (e.g. variants of the clock algorithm) might also be used 9.35 TLB (TRANSLATION LOOKASIDE BUFFERS) Achieving faster translations… cat: /app/work/document/fa5183488b964802b2239c9224486966.txt.output_35.text: No such file or directory 9.36 Page Table Performance • How many accesses to memory does it take to get the desired word that corresponds to the given virtual address? • So for each needed memory access, we need 2 additional? – That sounds BAD! • Would that change for a 1- or 3- level table? • M-level page table may require M memory accesses to find the translation…EXPENSIVE!! Offset w/in pageIndex 1 10 11 06 Index 2PDR First Level (Page Directory) Second Level 4K Page Desired word PPFN 210 * 4 bytes 210 * 4 bytes Virtual Address 9.37 Translation Unit / MMU Translation Lookaside Buffer (TLB) • Solution: Let’s create a cache for translations = Translation Lookaside Buffer (TLB) • Needs to be small (64-128 entries) so it can be fast, with high degree of associativity (at least 4-way and many times fully associative) to avoid conflicts – On hit, the PPFN is produced and concatenated with the offset – On miss, a page table walk is needed TLB I or D Cache CPU VA VPN Page Offset PPFN PA data10 ns 10 ns Memory Memory (Page Table) Hit M is s M is s Hit Processor 9.40 TLB + Data Cache Offset w/in page Virtual AddressVirtual Page Number 31 12 11 0 Page Frame # Offset w/in page Physical AddressPhys. Frame # 31 12 11 0 V MTag = VPN = = = = TLB Fully Direct Set-Assoc. 20 12 Phys. Tag Index Byte Offset Data Data Data DataTagV =Hit Desired Data 1416 TLB Data Cache Fully Direct Set-Assoc. MMU Cache If data cache is tagged with physical addresses, then we must translate the VA before we can access the data cache. 9.41 Differences of TLB & Data Cache • Data cache – 1 tag (to identify the block) corresponds to MANY bytes (16-64 bytes) • TLB – 1 tag (VPN) corresponds to 1 translation (PTE/PPFN) which is good for 4KB • Main Point: TLBs are smaller than normal data caches and faster to access TLB (1 tag = 1 translation. No Offset needed) Instruc./Data Cache (Offset needed since one tag corresponds to many values) 9.45 Cache, VM, and Main Memory TLB VM Cache Possible Y/N & Description Hit Hit Hit Possible: best-case scenario Hit Hit Miss Possible: TLB hits (hit in VM is implied), then cache miss Miss Hit Hit TLB misses, then hits in page table, then cache hit Miss Hit Miss TLB misses, then hits in page table, then cache miss Miss Miss Miss TLB misses, then page fault, then miss in cache Hit Miss Miss Impossible: cannot hit in TLB if page not present Hit Miss Hit Impossible: cannot hit in TLB if page not present Miss Miss Hit Impossible: data cannot be in cache if page not present Taken from H & P, “Computer Organization” 3rd, Ed. 9.46 x86 HW Cache/VM Support • Cache and TLB Configuration Processor Package Shared L3 Cache (8MB, 16-way) QuickPath Interconnect DDR3 Memory controller Core x4 Registers L1 D$ (32KB, 8-way) L2 Unified $ (256KB, 8-way)Instr. Fetch L1 I$ (32KB, 8-way) L1 iTLB (64 entry, 4-way) L1 dTLB (128 entry, 4-way) L2 Unified TLB (512 entry, 4-way) MMU Main Memory I/O Bridge Intel CoreTM i7 Memory System CR3/ PDBR 9.47 CoreTM i7 Page Table & Entries Format • Specs: 48-bit VA, 52-bit PA, 4KB pages, 4-level Page Table Level 1 (9-bits) Level 2 (9-bits) Level 3 (9-bits) Level 4 (9-bits) Page Offset (12-bits) CR3 L1 PTE L2 PTE L3 PTE L4 PTE Physical Page Number (40-bits) Page Offset (12-bits) L1 PT (Page Global Directory) L2 PT (Page Upper Directory) L3 PT (Page Middle Directory) L4 PT (Page Table) 512 GB range per PTE 1 GB range per PTE 2 MB range per PTE 4 KB range per PTE XD unused Physical Page number unused G unused D A CD WT U/S R/ W P=1 63 62-52 51 12 11 9 8 7 6 5 4 3 2 1 0 x86 Processor Core L4 PTE PTE Format XD (Execute Disable), G (Global Page), D (Dirty Bit), A (Referenced Bit), CD (Caching Disabled), WT (Write-Thru/WriteBack), U/S (User or Supervisor (Kernel) Mode Permission, R/W (Read-only or Read-write), P (Present/Valid). If P=0, all 63 other bits may be used as the OS desires to store information about the page (i.e. disk location, etc.) 9.50 IF TIME PERMITS Overlapping TLB access with Data/Instruction Cache access 9.51 Cache Addressing with VM • Review of cache – Store copies of data indexed based on the address they came from in MM – Simplified view: 2 steps to determine hit • Index: Hash portion of address to find "set" to look in • Tag match: Compare remaining address to all entries in set to determine hit – Sequential connection between indexing these two steps (index + tag match) • Rather than waiting for address translation and then performing this two step hit process, can we overlap the translation and portions of the hit sequence? – Yes if we choose page size, block size, and set/direct mapping carefully 0 1 2 3 4 … addr, data addr, data Index/HashTag Offset Address 9.52 Virtual vs. Physical Addressed Cache • Physically indexed, physically tagged (PIPT) – Wait for full address translation – Then use physical address for both indexing and tag comparison • Virtually indexed, physically tagged (VIPT) – Use portion of the virtual address for indexing then wait for address translation and use physical address for tag comparisons – Easiest when index portion of virtual address w/in offset (page size) address bits, otherwise aliasing may occur • Virtually indexed, virtually tagged (VIVT) – Use virtual address for both indexing and tagging…No TLB access unless cache miss – Requires invalidation of cache lines on context switch or use of process ID as part of tags Offset VAVPN 31 12 11 0 Offset PAPFN 31 12 11 0 Set/BlkTagP IP T Offset VAVPN 31 12 11 0 Offset PAPFN 31 12 11 0 Tag Set/Blk Offset VAVPN 31 12 11 0 Offset PAPFN 31 12 11 0 Set/BlkTag V IP T V IV T
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