Virtual Memory: Understanding the Use of Main Memory as a Cache for Secondary Storage, Study notes of Computer Science

Download Virtual Memory: Understanding the Use of Main Memory as a Cache for Secondary Storage and more Study notes Computer Science in PDF only on Docsity! 1 Lecture: Chp 7.4 Virtual Memory Memory Hierarchy CPU Core L1 Data L1 Instr L2 I&D MainMemory Disk Typically, on-chip $$$$, Fastest! $$$, Fast $$, Slow $, Slowest What Access Time SRAM 5-25 ns DRAM 60-120 ns Magnetic disk 10-20 million ns Larger memories Faster memories 2 Virtual Memory • The secondary storage (disk) is part of the memory hierarchy • Certainly, disks can hold files • But can we do more? ….. Yes! • Virtual memory: Treat main memory as a cache for secondary storage Virtual Memory Processor L2 Cache Physical Memory Disk Storage Virtual Memory 5 Virtual Memory Advantages to virtual memory: 1. Illusion of more main memory 2. More than one program can share memory 3. Program relocation 4. Protection Illusion of More Memory • Physical (main) memory space doesn’t have to be fully populated – E.g., 32 bit address space is 4 GB, but we don’t need that much actual main memory (modules) • The “virtual memory space” can be larger than the actual physical address space – E.g., virtual address space of 42 bits vs. actual main memory address space of 32 bits 6 Virtual Memory Physical Memory Disk Storage Virtual Memory The virtual memory address space is much larger than the physical memory address space More than One Program • Programs have own “virtual address space” • Virtual address space of each program is mapped to actual physical memory locations at run-time • Don’t need to know what programs will be running at same time when the programs are compiled 7 Virtual Memory Physical Memory Disk Storage Virtual Memory Two programs are mapped into physical memory Relocation • VM is an easy way to support relocation • Relocation: Program can be loaded into physical memory at different starting addresses each time the program is run - noncontiguous • Useful for multiprogramming - at run time, you don’t know what is running, so it’s hard to determine starting address permanently when program is compiled 10 Virtual Memory CODE DATA DATA CODE DATA DATA Physical Memory Disk Storage Virtual Memory Supposed you have a memory write to the virtual memory block marked as “code”. Virtual Memory WRITE DATA DATA WRITE DATA DATA Physical Memory Disk Storage Virtual Memory Supposed you have a memory write to the virtual memory block marked as “code”. Assuming no self-modifying code, that write shouldn’t be allowed 11 Virtual Memory Virtual addresses Physical memory caches part of the virtual space into a physical memory Disk storage contains the virtual address space Address translation physical addresses Processor generates the virtual address Virtual address translated into actual address in memory or possibly disk storage Virtual Memory Addresses Virtual memory with four virtual pages, where each page is 16 bytes big 12 Virtual Memory Addresses Virtual page number 0 Virtual page number 1 Virtual page number 2 Virtual page number 3 Virtual Memory Addresses Virtual page number 0 Virtual page number 1 Virtual page number 2 Virtual page number 3 Page offset selects a byte on a page 15 Some Terminology Similar to cache, but new terms: A page: Virtual memory block Page fault: A miss in main memory Physical memory: Locations in the main memory Virtual address: Mapped to physical location Address translation: From virtual to physical Virtual Memory Pages • Virtual memory page (vpage) is mapped to a page in physical memory (ppage) or disk • Translate the virtual address (VA) to physical address (PA) 3 2 1 011 10 9 815 14 13 1231 30 29 28 27 3 2 1 011 10 9 815 14 13 1229 28 27 Translation Virtual address Virtual page number page offset Physical page number page offset Physical address 16 Page Faults • What happens when vpage is on disk??? Page must be brought into memory! • Page fault: A vpage needed is not in memory but is on disk; I.e., a miss. • Page faults are expensive: – Millions of cycles for a disk access Consequences Large page sizes - amortize high cost – typical 4KB - 64KB Reduce page fault rate – fully associative structure Page faults handled by SW (the OS) – use clever algorithms; reduce page fault rate Use a write-back strategy – too expensive for write-through 17 Page Replacement • High page fault cost – Find ways to improve miss rate • Let OS place page any where in memory – Can be intelligent and pick page to replace that is mostly likely not needed again (soon) – Fully associative placement gives OS freedom to pick location Fully Associative Replacement • Expensive - requires searching for match – I.e., is a given vpage mapped to a ppage? • A better way - use a table lookup – So-called “page table” – One entry per vpage in the PT – Page table indexed by vpage number – (Yes, the table is large….) 20 Address Translation & the PT (1) HW uses PAR to find the process’ PT (2) In PT, find PTE for the given vpage (3) If PTE.valid == 1, page is in memory and use page to determine physical address (4) If PTE.valid == 0, page is on disk and must be loaded into memory (replacing an existing page mapped in memory) Page Faults • When virtual page is not mapped to a physical page, then OS gains control and loads that page into memory Two issues: (1) Where is vpage on the disk? (2) Where to place vpage in memory? 21 Finding a Page on Disk • OS keep tracks of disk location for page • Table similar to PT - indexed by vpage number to lookup disk location • The disk table may be included as part of the page table (I.e., a field is included for the disk location) Which Page to Replace • When bringing in a page, where is it placed in main memory? • Next unused physical page – OS keeps track of free main memory pages • No free physical page – Evict a page and replace it with the loaded one 22 Which Page to Replace • Minimize page faults, so intelligently pick the replaced page • LRU most common strategy E.g., page references: 10,12,9,7,11,10 Which is page is replaced? ….. 12 Pseudo-LRU • LRU is expensive, so hardware assistance is often provided • Use or reference bit - set whenever page is touched (referenced by a memory access) • Replace a page with its use bit set to 0 25 Page Tables can be Big Suppose a 32 bit virtual address & 4KB pages How big is the page table? Page offset 4KB = 212 Virtual page number 32 - 12 = 20 bits Total virtual pages 220 = 1M entries in PT ~4 bytes per PTE Then, 220 * 4B = 4MB for page table! Or, a total of 4 MB / 4KB = 1,024 pages! Fast Address Translation • Each memory reference requires two accesses to main memory: 1. Access page table in memory 2. Do actual memory access • How can we make this faster? Cache recently used page table entries! 26 Translation Look-aside Buffer • An on-chip cache that holds recently used page table entries (I.e., it caches recent address translations) Virtual space (on disk) Page tableMemory references (virtual address) TLB Physical address Physical memory Fast Address Translation Valid 1 1 1 1 0 1 1 0 1 1 0 1 Page table Physical page addressValid TLB 1 1 1 1 0 1 Tag Virtual page number Physical page or disk address Physical memory Disk storage Using a TLB 1. Check TLB 2. Hit - use translation 3. Miss - load TLB TLB Miss 1. OS trap (HW?) 2. Loads PTE into TLB 3. Replay access 4. Hits in the TLB TLB fully associative 27 TLBs • Relies on locality – If an access has locality, then the address translation also has locality – The address translations are cached by the TLB TLBs • A single address translation maps a page’s of memory addresses, so the TLB can be small – From 8-256 entries - quick access – Set associative or fully associative (small) • Separate instruction and data TLBs just like separate instruction and data caches