Download VLSI Design Process: Behavioral and Logic Synthesis and more Study notes Computer Science in PDF only on Docsity! 2002/4/29 Spring 2002 - Lecture #13 VLSI Design Methods & Tools © 2002 Dr. James P. Davis CSCE 613 Fundamentals of VLSI Design Page 2© 2002 Dr. James P. Davis Lecture 13 - Outline Introduction. This lecture provides an overview of the basic design methods and design tools used in the CMOS design process. Different methods and tools exist at each level of design abstraction. But several common properties emerge: We desire to maximize our speed through the design process, but must trade this off against accuracy of our results for a given design step. The more accuracy we desire, the greater the computational cost to obtain it. We can make simplifying assumptions about design representations using estimation, and then plug actual (more accurate) information in a later design step. We use iteration as a means to converge on an acceptable design pass. Design methods. Synthesis. Logic optimization. Technology mapping. Partition, place and route. Design capture & verification. Forms of design capture. Levels of design verification using simulation. Page 5© 2002 Dr. James P. Davis Overview of Behavioral Synthesis d <= a + b + c; d <= a + b + c; + + a b c d control step 1 control step 2 + + a b c d control step 1 + + a b d c s + MUX MUX s a b d c Behavioral synthesis starts with abstract description of behavior written in VHDL or C, no timing info. Task #1: Compile source code into intermediate format, for example, control-flow graph, dataflow graph. Task #2: schedule data operations to occur on specific control cycles, determined by clocking. Task #3: allocate data operations to RTL components implied by use of language operators <+, -, *...>. Task #4: bind specific operations to individual RTL components, to construct complete circuit topology. Page 6© 2002 Dr. James P. Davis Overview of Logic Synthesis Source: Synopsys Page 7© 2002 Dr. James P. Davis Logic Synthesis – Representation Levels Source: Synopsys Page 10© 2002 Dr. James P. Davis Logic Synthesis – Flat vs. Structured Structuring Add intermediate logic variables (i.e., logic structure) to a design block by creating sub-function units out of unstructured logic (could have been previously flattened). Result of structuring is that the expressions created as a result of intermediate terms results in shared logic, reducing terms in given logic equations, thus producing an area-efficient design. The tradeoff in structuring is that improved area may come at a cost in circuit delay, since additional logic structures are inserted in order to share the logic. Must be used carefully, as the designer can inadvertently add unneeded structure (particularly if used without flattening and minimization). Timing-driven structuring seeks to consider the critical path and timing constraints in the structuring process, usually by inserting redundant logic paths in order to minimize delay. Page 11© 2002 Dr. James P. Davis Logic Synthesis – Flat vs. Structured Flattening without Structuring Flattening with Structuring Flattening with Timing-driven Structuring Page 12© 2002 Dr. James P. Davis Optimization Technology-independent optimization: Network optimization (flattening and structuring) Two-level minimization (sum-of-products) Algebraic decomposition (structuring) Iterative improvement (extraction, factoring, substitution) Technology-dependent optimization: Technology optimizer “rule base” Directed Acyclic Graph (DAG) coverage Choose a “base function set” of gate structures. Create a “pattern gate” set by describing all logic gates in the library in terms of the base function set. Optimize the logic network in terms of the base function set gates, thus creating a “subject graph”. Apply graph optimization techniques to the subject graph.
