CS232: Computer Architecture II - Introduction, Study notes of Computer Architecture and Organization

Download CS232: Computer Architecture II - Introduction and more Study notes Computer Architecture and Organization in PDF only on Docsity! January 16, 2008 ©2006 Craig Zilles (adapted from slides by Howard Huang) 1 CS232: Computer Architecture II Fall 2007 January 16, 2008 Introduction to CS232 2  Computer architecture is about building and analyzing computer systems.  In CS232, we will take a tour of the whole machine.  Specifically, we’ll… What is computer architecture about? MemoryProcessor Input/Output CompilerHLL ASM January 16, 2008 Introduction to CS232 5  We’ll learn how to performance tune programs.  We’ll exploit explicit parallelism to make programs run faster — We’ll optimize a program using SSE instructions Learn about performance CompilerHLL ASM MemoryProcessor Input/Output January 16, 2008 Introduction to CS232 6  The key technique we’ll focus on is: Pipelining — Pipelining allows processors to work on multiple instructions at the same time. Learn about Modern Processor Organization Processor Memory Input/Output ASMCompilerHLL January 16, 2008 Introduction to CS232 7  We’ll learn how virtual memory makes programming easy  We’ll learn how caches make memory fast  We’ll learn about buses and disks Learn about Memory and I/O systems Processor Memory Input/Output CompilerHLL ASM January 16, 2008 Introduction to CS232 10 Who we are  Lecturer: Prof. Craig Zilles • I do research on computer architecture and compilers  Section Instructors & Teaching Assistants: Abhilasha Choudhary Abner Guzman Rivera Peter Young  Undergraduate Assistant: Brian James January 16, 2008 Introduction to CS232 11 How the class will be organized  The textbook provides the most comprehensive coverage  Lecture and section will present course material  Section problems useful for gauging your understanding of the material — Weekly, graded on effort, and good practice for the exams  Machine problems are more open-ended applications of course material — Due most weeks, graded, can be done in groups (1-3 people)  Homeworks used for closed-form, quantitative problems — Due occasionally, graded  Exams: three in-class midterms and one final  See the syllabus: http://www.cs.uiuc.edu/class/cs232/html/info.html  Questions? January 16, 2008 ©2006 Craig Zilles (partly adapted from slides by Howard Huang) 12  In CS232, we’ll talk about several important issues that we didn’t see in the simple processor from CS231. — The instruction set in CS231 lacked many features, such as support for function calls. We’ll work with a larger, more realistic processor. — We’ll also see more ways in which the instruction set architecture affects the hardware design. Instruction set architectures Software Hardware ISA January 16, 2008 Introduction to CS232 15 MIPS: register-to-register, three address  MIPS is a register-to-register, or load/store, architecture. — The destination and sources must all be registers. — Special instructions, which we’ll see later today, are needed to access main memory.  MIPS uses three-address instructions for data manipulation. — Each ALU instruction contains a destination and two sources. — For example, an addition instruction (a = b + c) has the form: add a, b, c operation destination sources operands January 16, 2008 Introduction to CS232 16 Register file review  Here is a block symbol for a general 2k × n register file. — If Write = 1, then D data is stored into D address. — You can read from two registers at once, by supplying the A address and B address inputs. The outputs appear as A data and B data.  Registers are clocked, sequential devices. — We can read from the register file at any time. — Data is written only on the positive edge of the clock. D data Write D address A address B address A data B data 2k × n Register File kk k n n n January 16, 2008 Introduction to CS232 17 MIPS register file  MIPS processors have 32 registers, each of which holds a 32-bit value. — Register addresses are 5 bits long. — The data inputs and outputs are 32-bits wide.  More registers might seem better, but there is a limit to the goodness. — It’s more expensive, because of both the registers themselves as well as the decoders and muxes needed to select individual registers. — Instruction lengths may be affected, as we’ll see in the future. D data Write D address A address B address A data B data 32 × 32 Register File 55 5 32 32 32 January 16, 2008 Introduction to CS232 20  More complex arithmetic expressions may require multiple operations at the instruction set level. t0 = (t1 + t2) × (t3 − t4) add $t0, $t1, $t2 # $t0 contains $t1 + $t2 sub $s0, $t3, $t4 # Temporary value $s0 = $t3 - $t4 mul $t0, $t0, $s0 # $t0 contains the final product  Temporary registers may be necessary, since each MIPS instructions can access only two source registers and one destination. — In this example, we could re-use $t3 instead of introducing $s0. — But be careful not to modify registers that are needed again later. Larger expressions January 16, 2008 Introduction to CS232 21 Immediate operands  The ALU instructions we’ve seen so far expect register operands. How do you get data into registers in the first place? — Some MIPS instructions allow you to specify a signed constant, or “immediate” value, for the second source instead of a register. For example, here is the immediate add instruction, addi: addi $t0, $t1, 4 # $t0 = $t1 + 4 — Immediate operands can be used in conjunction with the $zero register to write constants into registers: addi $t0, $0, 4 # $t0 = 4  MIPS is still considered a load/store architecture, because arithmetic operands cannot be from arbitrary memory locations. They must either be registers or constants that are embedded in the instruction. January 16, 2008 Introduction to CS232 22 A more complete example  What if we wanted to compute the following? 1 + 2 + 3 + 4 January 16, 2008 Introduction to CS232 25 MIPS memory  MIPS memory is byte-addressable, which means that each memory address references an 8-bit quantity.  The MIPS architecture can support up to 32 address lines. — This results in a 232 x 8 RAM, which would be 4 GB of memory. — Not all actual MIPS machines will have this much! 232 × 8 memory ADRS OUT DATA CS WR 832 8 0 1 2 3 4 5 6 7 8 9 10 11Address 8-bit data January 16, 2008 Introduction to CS232 26 Loading and storing bytes  The MIPS instruction set includes dedicated load and store instructions for accessing memory, much like the CS231 example processor.  The main difference is that MIPS uses indexed addressing. — The address operand specifies a signed constant and a register. — These values are added to generate the effective address.  The MIPS “load byte” instruction lb transfers one byte of data from main memory to a register. lb $t0, 20($a0) # $t0 = Memory[$a0 + 20]  The “store byte” instruction sb transfers the lowest byte of data from a register into main memory. sb $t0, 20($a0) # Memory[$a0 + 20] = $t0 January 22, 2003 Introduction to CS232 27 Byte loads  Question: if you load a byte (8 bits) into a register (32 bits), what value do those other 24 bits have? January 16, 2008 Introduction to CS232 30  So, to compute with memory-based data, you must: 1. Load the data from memory to the register file. 2. Do the computation, leaving the result in a register. 3. Store that value back to memory if needed.  For example, let’s say that you wanted to do the same addition, but the values were in memory. How can we do the following using MIPS assembly language? char A[4] = {1, 2, 3, 4}; int result; result = A[0] + A[1] + A[2] + A[3]; Computing with memory January 16, 2008 Introduction to CS232 31 Memory alignment  Keep in mind that memory is byte-addressable, so a 32-bit word actually occupies four contiguous locations (bytes) of main memory.  The MIPS architecture requires words to be aligned in memory; 32-bit words must start at an address that is divisible by 4. — 0, 4, 8 and 12 are valid word addresses. — 1, 2, 3, 5, 6, 7, 9, 10 and 11 are not valid word addresses. — Unaligned memory accesses result in a bus error, which you may have unfortunately seen before.  This restriction has relatively little effect on high-level languages and compilers, but it makes things easier and faster for the processor. 0 1 2 3 4 5 6 7 8 9 10 11 Word 1 Word 2 Word 3 Address 8-bit data January 22, 2003 Introduction to CS232 32 Next time  Our next topic is control flow in MIPS — On Friday, we’ll introduce loops. — Next Wednesday, we’ll show if/then/else structures.